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ISO808ATR中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

ISO808ATR
廠商型號(hào)

ISO808ATR

功能描述

Galvanic isolated octal high-side power solid state relay with SPI interface for high inductive loads

文件大小

1.7236 Mbytes

頁(yè)面數(shù)量

38 頁(yè)

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-1 23:00:00

ISO808ATR規(guī)格書(shū)詳情

Features

? VCC(AMR) = 45 V

? Wide process side op. range VCC = 9.2 to 36 V

? RDS(on) = 0.125 Ω per channel (TYP)

? Fast demagnetization of inductive loads VDEMAG(TYP) = VCC - 54 V

? Per channel process side op. current

– ISO808A IOUT < 0.7 A

– ISO808A-1 IOUT < 1 A

? Low process and logic sides supply current

? Under-voltage shut down with auto restart and hysteresis

? Logic side 5 V and 3.3 V TTL/CMOS and MCU compatible I/Os

? Logic side SPI interface

? Common output enable/disable pin

? Reset function for IC outputs disable

? High common mode transient immunity

? Short circuit protection on output channels

– ISO808A ILIM(MIN) = 0.7 A

– ISO808A ILIM(MIN) = 1 A

? Per-channel over-temperature protection with thermal independence of

separate channels

? Case over-temperature protection

? Over-voltage protection (VCC clamping)

? Loss of GND and VCC protections

? Common fault open drain diagnostic

? VCC Power Good open drain diagnostic

? Designed to meet IEC 61000-4-2, IEC 61000- 4-4, IEC 61000-4-5 and IEC

61000-4-8

? UL1577 and UL508 certified

? PowerSO-36 Package

Applications

? Programmable logic control

? Industrial PC peripheral input/output

? Numerical control machines

? Drivers for all type of loads (resistive, capacitive, inductive)

Description

The ISO808A, ISO808A-1, are galvanic isolated 8-channel drivers featuring a low supply current. Each driver

contains 2 independent galvanic isolated voltage domains (VCC and VDD for the Process and Control Logic

stages, respectively). The ICs are intended for driving any kind of load with one side connected to ground.

The Control Logic Stage features an 8-bit Output Status Register (where the MCU sets the ON/OFF status of

the output channels in the Process Stage), daisy chaining is allowed. The two stages communicate through the

galvanic isolation channel by an ST proprietary protocol.

Active channel current limitation (OVL) combined with thermal shutdown (OVT), independent for each channel,

protects the device against overload.

Built-in thermal shut down protects each channel from over-temperature and overload: each overheated channel

automatically turns OFF after its junction temperature triggers the protection threshold (TJSD). The channel turns

back ON if its junction temperature decreases lower than restart threshold (TJR).

An additional case temperature sensor protects the whole chip against over-temperature (OVC event): if the case

temperature triggers the TCSD threshold then overloaded channels are turned OFF and will restart only when case

temperature decreased down to the reset threshold (TCR). Non overloaded channels continue to operate normally.

Other embedded functions are loss of ground protection, VCC and VDD UVLOs (with hysteresis), watchdog and

VCC Power GOOD.

An internal circuit provides an OR-wired not latched common FAULT indicator signaling the channel OVT. The

PGOOD diagnostic pin is activated if VCC goes below the power good threshold. Both FAULT and PGOOD pins

are open drain, active low, fault indication pins.

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3001
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8860
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65
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