IMSA110-G20S中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

. 1-D/2-D SOFTWARE CONFIGURABLE CON VOLVER/FILTER

. ON-CHIP PROGRAMMABLE LINE DELAYS (0 — 1120 STAGES)

. 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE

. 21 MULTIPLY-AND-ACCUMULATE STAGES

. 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW

. ON-CHIP POST PROCESSOR FOR DATA TRANSFORMATION

. FULLY CASCADABLE IN WINDOW SIZE AND ACCURACY

. 20 MHZ DATA THROUGHPUT (420 MOPS)

. SIGNED/UNSIGNED DATA AND COEFFICIENTS

. MICROPROCESSOR INTERFACE

. HIGH SPEED CMOS IMPLEMENTATION

. TTL COMPATIBLE

. SINGLE +5V ± 10 SUPPLY

. POWER DISSIPATION < 2.0 WATTS

. 100 PIN CERAMIC PGA

APPLICATIONS

. 1-D and 2-D digital convolution and correlation

. Real time image processing and enhancement

. Edge and feature detection

. Data transformation and histogram equalisation

. Computer vision and robotics

. Template matching

. Pulse compression

. 1-D or 2-D interpolation