IDT72V3624中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION:

The IDT72V3624/72V3634/72V3644 are pin and functionally compatible versions of the IDT723624/723634/723644, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or LittleEndian configurations.

FEATURES:

? Memory storage capacity:

IDT72V3624–256 x 36 x 2

IDT72V3634–512 x 36 x 2

IDT72V3644–1,024 x 36 x 2

? Clock frequencies up to 100 MHz (6.5ns access time)

? Two independent clocked FIFOs buffering data in opposite directions

? Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions)

? Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64)

? Serial or parallel programming of partial flags

? Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)

? Big- or Little-Endian format for word and byte bus sizes

? Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

? Mailbox bypass registers for each FIFO

? Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)

? Auto power down minimizes power dissipation

? Available in space saving 128-pin Thin Quad Flatpack (TQFP)

? Pin and functionally compatible version of the 5V operating IDT723624/723634/723644

? Industrial temperature range (–40°C to +85°C) is available