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ICS8521I-03中文資料ICST數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
ICS8521I-03 |
| 功能描述 | LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER |
| 文件大小 |
135.17 Kbytes |
| 頁(yè)面數(shù)量 |
15 頁(yè) |
| 生產(chǎn)廠商 | Integrated Circuit Systems |
| 企業(yè)簡(jiǎn)稱 |
ICST |
| 中文名稱 | Integrated Circuit Systems官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-8-2 11:52:00 |
| 人工找貨 | ICS8521I-03價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
ICS8521I-03規(guī)格書詳情
GENERAL DESCRIPTION
The ICS8521I-03 is a low skew, 1-to-9 Differential-to-LVHSTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS8521I-03 has two selectable clock inputs. Redundant clock pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
FEATURES
? 9 LVHSTL outputs
? Redundant differential CLK0, nCLK0 and CLK1, nCLK1 inputs
? CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
? Maximum output frequency: 500MHz
? Output skew: 50ps (maximum)
? Part-to-part skew: 250ps (maximum)
? Propagation delay: 1.6ns (maximum)
? VOH = 1V (maximum)
? 3.3V core, 1.8V output operating supply voltages
? -40°C to 85°C ambient operating temperature
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
IDT |
21+ |
TSSOP20 |
12588 |
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SOP8 |
193 |
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2025+ |
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3625 |
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ICS |
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6528 |
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22+ |
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5000 |
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詢價(jià) | ||
IDT |
21+ |
SOP8 |
10000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) |
