HM62G18512中文資料日立數據手冊PDF規(guī)格書

Description

The HM62G18512 is a synchronous fast static RAM organized as 512-kword × 18-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features

? Power supply: 3.3 V +10, –5

? Clock frequency: 200 MHz to 250 MHz

? Internal self-timed late write

? Byte write control (2 byte write selects, one for each 9-bit)

? Optional ×36 configuration

? HSTL compatible I/O

? Programmable impedance output drivers

? User selective input trip-point

? Differential, HSTL clock inputs

? Asynchronous G output control

? Asynchronous sleep mode

? Limited set of boundary scan JTAG IEEE 1149.1 compatible

? Protocol: Single clock register-register mode