HLQFP144中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

2.1 Hardware features

SAF7741HV hardware is configured by firmware and host software to meet specific

customer requirements. The firmware is defined by the Read-Only Memory ROM code

associated with each DSP.

Remark: The list below describes the maximum hardware configuration. Customers

should consult with NXP to identify the best method of supporting their own particular

requirements.

- Two IF data-paths of either 2 x IF 10.7 MHz or 2 x low IF 300 kHz input

Remark: The combination of 1 x IF and 1 x low IF is not supported.

- Two 5th order Sigma-Delta IF ADCs for FM/AM/WB Weather-band and digital

- AGC control of the TEF6730 tuner front-end PIN diodes, with an analog signal via the

data-path

- Two Radio Data System decoders

- Five bit-stream, 3rd order audio, ADCs with an anti-aliasing broadband input-filter

- Eight configurable analog inputs connected to any of the five

ADCs using an analog switchbox

- Dedicated DSP for the Sample Rate Converter

- Audio Host Inter-IC Sound Input/Output port, with eight/ten outputs and eight

inputs with an option for slaving the DSP to an external master sample-rate

- Audio Host IIS Bit-Clock and Word-Size available simultaneously at

full-rate and half-rate

- Four independent IIS inputs and two independent digital Sony/Philips Digital Interface

Format inputs also configurable for Digital Versatile Disc/Digital Video Device multi-channel data inputs

- Radio Host IIS master with separate data in and out lines

- IIS output with buffer for eight samples for radio applications

- WatchDog WDOG to monitor execution of the DSP main software loop

- Phase-Lock Loop PLL to generate the DSP clock from the oscillator crystal

- PLL to generate the audio reference sample-rate clock

- Internal voltage regulator for the 1.8 V supply

- I2C Inter-IC Communication bus-controlled

- Possibility of powering down unused blocks to reduce power dissipation

- Qualified in accordance with AEC-Q100