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HD74HC377FPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書
HD74HC377FPEL規(guī)格書詳情
Description
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuitsare designed to prevent false clocking by transitions at the G input.
Features
? High Speed Operation: tpd= 13 ns typ (CL= 50 pF)
? High Output Current: Fanout of 10 LSTTL Loads
? Wide Operating Voltage: VCC= 2 to 6 V
? Low Input Current: 1 μA max
? Low Quiescent Supply Current: ICC(static) = 4 μA max (Ta = 25°C)
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
只做原裝 |
21+ |
SOP-20 |
36520 |
一級(jí)代理/放心采購 |
詢價(jià) | ||
RENESAS/瑞薩 |
22+ |
DIP14 |
50000 |
原裝正品.假一罰十 |
詢價(jià) | ||
HITACHI/日立 |
24+ |
SOP |
860000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價(jià) | ||
RENESAS |
22+ |
SOP-0.52 |
8000 |
原裝正品支持實(shí)單 |
詢價(jià) | ||
HIT |
23+ |
SOIC-14/5.2m |
3200 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售 |
詢價(jià) | ||
HIT |
24+ |
DIP |
5371 |
詢價(jià) | |||
HIT |
23+ |
SOP |
7000 |
絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購! |
詢價(jià) | ||
HITACHI |
1733+ |
SOP14 |
6528 |
只做進(jìn)口原裝正品假一賠十! |
詢價(jià) | ||
HIT |
22+ |
SOIC-14/5.2m |
1000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價(jià) | ||
HIT |
96+ |
SOIC/5.2mm |
1351 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
詢價(jià) |
