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HD3-15530-9中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書
HD3-15530-9規(guī)格書詳情
Description
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for
the Master Reset functions.
This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmental control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Features
? Support of MlL-STD-1553
? Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
? Sync Identification and Lock-In
? Clock Recovery
? Manchester II Encode, Decode
? Separate Encode and Decode
? Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
產(chǎn)品屬性
- 型號:
HD3-15530-9
- 制造商:
INTERSIL
- 制造商全稱:
Intersil Corporation
- 功能描述:
CMOS Manchester Encoder-Decoder
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
POWER GENERAL |
2015 |
模塊 |
300 |
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TI/德州儀器 |
23+ |
VQNN20 |
10000 |
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HBA |
LQFP64 |
53650 |
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詢價 | |||
POWERGENE |
24+ |
2173 |
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詢價 | |||
HL |
22+ |
DIP-8 |
5000 |
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詢價 | ||
HITACHI/日立 |
2022 |
DIP |
80000 |
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詢價 | ||
HIT |
23+ |
DIP28 |
27888 |
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REALTEK(瑞昱) |
22+ |
QFN-24 |
50 |
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22+ |
DIP-16 |
9600 |
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詢價 | ||
HITACHI/日立 |
22+ |
DIP-16 |
6550 |
原裝 低價 支持實(shí)單 |
詢價 |