GTLP16612MEA集成電路（IC）的通用總線功能規(guī)格書PDF中文資料

General Description

The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times.

Features

■ Bidirectional interface between GTLP and TTL logic

levels

■ Designed with Edge Rate Control Circuit to reduce

output noise

■ VREF pin provides external supply reference voltage for

receiver threshold

■ Submicron Core CMOS technology for low power

dissipation

■ Special PVT Compensation circuitry to provide consistent

performance over variations of process, supply

voltage and temperature

■ 5V tolerant inputs and outputs on A-Port

■ Bus-Hold data inputs on A-Port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down high impedance

■ TTL compatible Driver and Control inputs

■ A-Port outputs source/sink ?32 mA/+32 mA

■ Flow-through architecture optimizes PCB layout

■ Open drain on GTLP to support wired-or connection