GS9002ACPME3中文資料根努姆數(shù)據(jù)手冊PDF規(guī)格書

DEVICE DESCRIPTION

The GS9002A is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines.

FEATURES

? fully compatible with SMPTE-259M serial digital standard

? supports up to four serial bit rates to 400 Mb/s

? accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs

? X9 + X4 + 1 scrambler, NRZI converter and sync detector may be disabled for transparent data transmission

? pseudo-ECL serial data and clock outputs

? single +5 or -5 volt supply

? 713 mW typical power dissipation (including ECL pull-down loads).

? 44 pin PLCC packaging

? Pb-free and Green

APPLICATIONS

? 4?SC, 4:2:2 and 360 Mb/s serial digital interfaces for Video cameras, VTRs, Signal generators