F369GA中文資料富士通數(shù)據(jù)手冊(cè)PDF規(guī)格書

■ DESCRIPTION

The MB91360G series is a standard microcontroller containing a wide range of I/O peripherals and bus control functions. The MB91360G series features a 32-bit RISC CPU (FR50) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. Also, Internal memories to improve the execution speed of the CPU.

■ FEATURES

? Execution time : down to 15.6 ns (64 MHz)

? FR50 CPU : RISC architecture

The CPU has a general-purpose register architecture with improved numeric implementation whereby a wide

range of delayed branch instructions reduces losses in execution time due to pipeline breaks.

Bit manipulation instructions and memory access instructions have been enhanced resulting in improved code

efficiency and execution speed for control implementation.

? A five-stage pipeline structure provides high-speed processing (one instruction per cycle)

? 32-bit linear address space : 4 Gbytes

? Fixed 16-bit instruction size (basic instructions)

? High-speed multiplication/step division

? High-speed interrupt processing (6 cycles)

? General-purpose registers : 16 × 32 bits

? External bus interface unit with a wide range of functions

Divides the external memory space into a maximum of eight areas. Chip select signal setting, data bus width

selection (8, 16, 32-bit) , and area size can be specified for each area.

? Address bus up to 32 bit wide

? Programmable auto-wait function

? DMAC

Direct memory access (DMA) can be used to perform various types of data transfer without going via the CPU.

This improves system performance.

? Eight channels (including up to 3 external channels)

? Four transfer modes supported : single/block, burst, continuous transfer, and fly-by

? Power consumption control mechanisms

The MB91360G series contains a number of functions for controlling the operating clock to reduce power

consumption.

? Software control : Sleep and stop/real time clock functions

? Hardware control : Hardware standby function

? Gear (divider) function : The CPU and peripheral clock frequencies can be set independently.

? Contains a range of peripheral functions

? UART, U-timer

? Real Time Clock (with optional subclock operation and subclock calibration module)

? Stepper Motor Control

? Sound Generator

? Serial I/O (SIO) , SIO-Prescaler

? Power Down Reset

? Alarm Comparator

? I/O-Timer

? I2C Interface

? 10-bit D/A Converter

? CAN Interface

? 10-bit A/D converter

? 16-bit reload timer

? 16-bit PWM timer

? Watchdog timer

? Bit search module

? Interrupt controller

? External interrupt inputs

? I/O port function

? Interrupt levels

“16 maskable interrupt levels”

? Other

? Power supply voltage

? 5 V power supply used, the internal regulator creates internal supply of 3.3 V

? Package : MB91FV360GA uses a PGA401 package, MB91F362GB is delivered in a QFP208 package, and

MB91F369GA in QFP160 package.

MB91F364G, MB91F365GB, MB91F366GB, MB91F367GB, MB91F368GB, MB91366GA and MB91F376G

will be delivered in an LQFP120 package.

(See also section ■ PACKAGE DIMENSIONS. )