DESCRIPTION

The ETC5057/ETC5054 family consists of A-law and μ–law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM interface. The devices are fabricated using doublepoly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law or μ–law PCM format.

■ COMPLETE CODEC AND FILTERING SYSTEM (DEVICE) INCLUDING:

– Transmit high-pass and low-pass filtering.

– Receive low-pass filter with sin x/x correction.

– Active RC noise filters

– μ-law or A-law compatible COder and DECoder.

– Internal precision voltage reference.

– Serial I/O interface.

– Internal auto-zero circuitry.

■ A-LAW 16 PINS (ETC5057FN, 20 PINS)

■ μ-LAW WITHOUT SIGNALING, 16 PINS (ETC5054FN, 20 PINS)

■ MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS

■ ±5V OPERATION

■ LOW OPERATING POWER - TYPICALLY 60 mW

■ POWER-DOWN STANDBY MODE - TYPICALLY 3 mW

■ AUTOMATIC POWER-DOWN

■ TTL OR CMOS COMPATIBLE DIGITAL INTERFACES

■ MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY

■ 0 to 70°C OPERATION

ETC5054N屬于集成電路（IC） > 編解碼器。意法半導(dǎo)體（ST）集團(tuán)制造生產(chǎn)的ETC5054N編解碼器編解碼器是用于通過壓縮和解壓縮來轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲空間。某些編解碼器提供高達(dá) 32 位的分辨率，并且分別提供多達(dá) 6 個(gè)或 8 個(gè)模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。