DS320PR810開發(fā)板套件編程器的評估演示板及套件規(guī)格書PDF中文資料

1 Features

? Eight-channel linear redriver supporting PCIe 5.0,

CXL 2.0, UPI 2.0 up to 32 Gbps

? Supports most ac coupled interfaces including DP,

SAS, SATA, XFI

? CTLE boosts up to 22 dB at 16 GHz

? Ultra-low latency of 100 ps

? Low additive random jitter of 75 fs for PRBS data

? Excellent return loss of -10 dB at 16 GHz

? Single 3.3 V supply

? Internal voltage regulator provides immunity to

supply noise

? Low active power of 160 mW / channel

? No heat sink required

? Pin-strap, SMBus or EEPROM programming

? Automatic receiver detection for PCIe use cases

? Protocol agnostic linear redriver allows seamless

support for PCIe link training

? Support for x4, x8, x16, x24 bus width with one or

multiple DS320PR810

? Temperature range of –40 °C to 85 °C

? 5.5 mm × 10 mm, 64 pin WQFN package

2 Applications

? Rack server, and microserver and tower server

? High performance computing

? Hardware accelerator

? Network attached storage

? Storage area network (SAN) and host bus adapter

(HBA) card

? Network interface card (NIC)

? Desktop PC/motherboard

3 Description

The DS320PR810 is an eight channel low-power

high-performance linear repeater or redriver designed

to support PCIe 5.0, CXL 2.0, UPI 2.0, and other

interfaces up to 32 Gbps.

The DS320PR810 receivers deploy continuous time

linear equalizers (CTLE) to provide a programmable

high-frequency boost. The equalizer can open an

input eye that is completely closed due to intersymbol

interference (ISI) induced by an interconnect

medium, such as PCB traces. The CTLE receiver

is followed by a linear output driver. The linear datapaths

of DS320PR810 preserve transmit preset signal

characteristics. The linear redriver becomes part of

the passive channel that as a whole get link trained

for best transmit and receive equalization settings.

This transparency in the link training protocol results

in best electrical link and lowest possible latency.

Low channel-channel cross-talk, low additive jitter

and excellent return loss makes the device almost

a passive element in the link, but with its useful

equalization. The data-path of the device uses an

internally regulated power rail that provides high

immunity to any supply noise on the board.

The device also has low AC and DC gain variation

providing consistent equalization in high volume

platform deployment.