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CY7C1371D-133BGXI

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGXI

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133AXC

18-Mbit(512K?36/1M?18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133AXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133AXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133AXI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133AXI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGC

18-Mbit(512K?36/1M?18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BGXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZI

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBL??Architecture

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

CY7C1371D-133BZXC

18-Mbit(512Kx36/1Mx18)Flow-ThroughSRAMwithNoBLTMArchitecture

FunctionalDescription[1] TheCY7C1371D/CY7C1373Disa3.3V,512Kx36/1Mbitx18SynchronousFlow-throughBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1371D/CY7C1373DisequippedwiththeadvancedNo

CypressCypressSemiconductor

賽普拉斯賽普拉斯半導(dǎo)體公司

供應(yīng)商型號品牌批號封裝庫存備注價格
CYPRESS
2138+
原廠標(biāo)準(zhǔn)封裝
8960
代理CYPRESS全系列芯片,原裝現(xiàn)貨
 詢價
CYPRESS/賽普拉斯
22+
BGA
12245
現(xiàn)貨,原廠原裝假一罰十!
 詢價
CYPRESS/賽普拉斯
22+
BGA
50000
只做原裝正品,假一罰十,歡迎咨詢
 詢價
CYPRESS/賽普拉斯
23+
BGA
6000
專業(yè)配單保證原裝正品假一罰十
 詢價
Cypress
22+
100TQFP (14x20)
9000
原廠渠道,現(xiàn)貨配單
 詢價
Cypress
21+
100TQFP (14x20)
13880
公司只售原裝,支持實(shí)單
 詢價
Cypress
23+
100TQFP (14x20)
9000
原裝正品，支持實(shí)單
 詢價
Cypress
23+
100-TQFP(14x20)
9550
專業(yè)分銷產(chǎn)品!原裝正品!價格優(yōu)勢!
 詢價
CYPRESS
22+
TQFP
10000
原裝正品優(yōu)勢現(xiàn)貨供應(yīng)
 詢價
最新
2000
原裝正品現(xiàn)貨
 詢價
更多CY7C1371D-133BGXI供應(yīng)商 更新時間2024-11-15 14:07:00

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