CY2308SI-3集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications.

The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven into the FBK pin and obtained from one of the outputs. The input-to-output skew is less than 350 ps and output-to-output skew is less than 200 ps.

Features

■ Zero input-output propagation delay, adjustable by capacitive load on FBK input

■ Multiple configurations, see “Available CY2308 Configurations” on page 3

■ Multiple low skew outputs

■ Two banks of four outputs, three-stateable by two select inputs

■ 10 MHz to 133 MHz operating range

■ 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

■ Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP

■ 3.3V operation

■ Industrial Temperature available