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CS4207-CNZSLASHC1中文資料凌云邏輯數(shù)據(jù)手冊PDF規(guī)格書

CS4207-CNZSLASHC1
廠商型號

CS4207-CNZSLASHC1

功能描述

Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp

文件大小

819.46 Kbytes

頁面數(shù)量

144

生產(chǎn)廠商 Cirrus Logic
企業(yè)簡稱

CIRRUS凌云邏輯

中文名稱

凌云邏輯官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-6-9 14:26:00

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CS4207-CNZSLASHC1規(guī)格書詳情

General Description

The CS4207 is a highly integrated multi-channel low power HD Audio Codec featuring 192 kHz DACs, 96 kHz ADCs, 192 kHz S/PDIFTransmitters and Receiver, Microphone pre-amp and bias voltage, and a ground centered Headphone driver. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 32 kHz and 192 kHz.

DIGITAL to ANALOG FEATURES

DAC1 (Headphone)

– 101 dB Dynamic Range (A-wtd)

– -89 dB THD+N

Headphone Amplifier - GND Centered

– Integrated Negative-voltage Regulator

– No DC-blocking Capacitor Required

– 50 mW Power/Channel into 16?

DAC2 & DAC3 (Line Outs)

– 110 dB Dynamic Range (A-wtd)

– -94 dB THD+N

– Differential Balanced or Single-ended

Each DAC Supports 32 kHz to 192 kHz Sample Rates Independently.

Digital Volume Control

– +6.0 dB to -57.5 dB in 0.5 dB Steps

– Zero Cross and/or Soft Ramp Transitions

Independent Support of D0 and D3 Power States for Each DAC

Fast D3 to D0 Transition

– Audio Playback in Less Than 50 ms

ANALOG to DIGITAL FEATURES

ADC1 & ADC2

– 105 dB Dynamic Range (A-wtd)

– -88 dB THD+N

– Differential Balanced or Single-ended Inputs

– Analog Programmable Gain Amplifier (PGA) ±12 dB, 1.0 dB Steps, with Zero Cross Transitions and Mute

MIC Inputs

– Pre-amplifier with Selectable 0 dB, +10 dB, +20 dB, and +30 dB Gain Settings

– Programmable, Low-noise MIC Bias Level

Each ADC Supports 8 kHz to 96 kHz Sample Rates Independently

Additional Digital Attenuation Control

– -13.0 dB to -51.0 dB in 1.0 dB steps

– Zero Cross and/or Soft Ramp Transitions

Digital Interface for Two Dual Digital Mic Inputs

Independent Support of D0 and D3 Power States for Each ADC

System Features

Very Low D3 Power Dissipation of <7 mW

– Jack Detect Active in D3

– HDA BITCLK Not Required for D3 State

Jack Detect Does Not Require HDA Bus BITCLK

All Configuration Settings are Preserved in D3 State

Pop/Click Suppression in State Transitions

Detects Wake Event and Generates Power State Change Request when HDA Bus Controller is in D3

Variable Power Supplies

– 1.5 V to 1.8 V Digital Core Voltage

– 3.3 V to 5.0 V Analog Core Voltage

– 3.3 V to 5.0 V Headphone Drivers

– 1.5 V to 3.3 V HD Bus Interface Logic

– 3.3 V Interface Logic levels for GPIO, S/PDIF, and Digital Mic

Individual Power-down Managed

– ADCs, DACs, PGAs, Headphone Driver, S/PDIF Receiver, and Transmitters

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25+
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原裝正品,假一罰十!
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