CD74HC4017QPWREP集成電路（IC）的計數(shù)器除法器規(guī)格書PDF中文資料

CD74HC4017QPWREP屬于集成電路（IC）的計數(shù)器除法器。由美國德州儀器公司制造生產(chǎn)的CD74HC4017QPWREP計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應(yīng)用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應(yīng)用。

Controlled Baseline

? One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

?40°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree?

Fully Static Operation

Buffered Inputs

Common Reset

Positive Edge Clocking

Typical fmax = 60 MHz at VCC = 5 V,

CL = 15 pF, TA = 25°C

Fanout (Over Temperature Range)

? Standard Outputs . . . 10 LSTTL Loads

? Bus Driver Outputs . . . 15 LSTTL Loads

Balanced Propagation Delay and Transition

Times

Significant Power Reduction Compared to

LSTTL Logic ICs

VCC Voltage = 2 V to 6 V

High Noise Immunity NIL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each

of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of

the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and

can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting

when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded

outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.