CD74HC4017PW集成電路（IC）的計(jì)數(shù)器除法器規(guī)格書PDF中文資料

CD74HC4017PW屬于集成電路（IC）的計(jì)數(shù)器除法器。由美國德州儀器公司制造生產(chǎn)的CD74HC4017PW計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

Features

? Fully Static Operation

? Buffered Inputs

? Common Reset

? Positive Edge Clocking

? Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC

? Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

? Wide Operating Temperature Range . . . -55oC to 125oC

? Balanced Propagation Delay and Transition Times

? Significant Power Reduction Compared to LSTTL

Logic ICs

? HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

Description

The ’HC4017 is a high speed silicon gate CMOS 5-stage

Johnson counter with 10 decoded outputs. Each of the

decoded outputs is normally low and sequentially goes high

on the low to high transition clock period of the 10 clock

period cycle. The CARRY (TC) output transitions low to high

after OUTPUT 10 goes from high to low, and can be used in

conjunction with the CLOCK ENABLE (CE) to cascade

several stages. The CLOCK ENABLE input disables

counting when in the high state. A RESET (MR) input is also

provided which when taken high sets all the decoded

outputs, except “0”, low.

The device can drive up to 10 low power Schottky equivalent

loads.