Features

? Dedicated clock buffer power pins for reduced noise, crosstalk and jitter

? Input clock frequency of 25 MHz to 33.3 MHz

? Output frequencies of XINx1, XINx2, XINx3 and XINx4

? Output grouped in two banks of five clocks each

? One REF XIN clock output

? SMBus clock control interface for individual clock disabling and SSCG control and individual back frequency selection

? Output clock duty cycle is 50 (± 5)

? < 250 ps skew between output clocks within a bank

? Output jitter < 250 psec (175 psec with all outputs at the same frequency)

? Spread Spectrum feature for reduced electromagnetic interference (EMI)

? OE pins for entire output bank enable control and testability

? 48-pin SSOP and TSSOP packages