ATF1502ASL-25JI84中文資料愛特梅爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The ATF1502AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switchmatrices increase usable gate count and the odds of successful pin-locked design modifications.

Features

? High-density, High-performance, Electrically-erasable Complex Programmable Logic Device

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

? In-System Programmability (ISP) via JTAG

? Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

? Advanced Power Management Features

? Automatic 10 μA Standby for “L” Version

? Pin-controlled 1 mA Standby Mode

? Programmable Pin-keeper Inputs and I/Os

? Reduced-power Feature per Macrocell

? Available in Commercial and Industrial Temperature Ranges

? Available in 44-lead PLCC and TQFP

? Advanced EEPROM Technology

– 100 Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

? JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

? PCI-compliant

? Security Fuse Feature

? Green (Pb/Halide-fee/RoHS Compliant) Package Options

Enhanced Features

? Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

? Output Enable Product Terms

? D Latch Mode

? Combinatorial Output with Registered Feedback within Any Macrocell

? Three Global Clock Pins

? ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)

? Fast Registered Input from Product Term

? Programmable “Pin-keeper” Option

? VCCPower-up Reset Option

? Pull-up Option on JTAG Pins TMS and TDI

? Advanced Power Management Features

– Input Transition Detection

– Power-down (“L” Versions)

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O