AT52BC3221A中文資料愛特梅爾數(shù)據(jù)手冊PDF規(guī)格書

Description

The AT52BC3221A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit PSRAM (organized as 512K x 16) in a stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the extended temperature range.

Features

? 32-Mbit Flash and 4-Mbit/8-Mbit PSRAM

? Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package

? 2.7V to 3.3V Operating Voltage

Flash

? 32-megabit (2M x 16)

? 2.7V to 3.3V Read/Write

? Access Time – 70 ns

? Sector Erase Architecture

– Sixty-three 32K Word Sectors with Individual Write Lockout

– Eight 4K Word Sectors with Individual Write Lockout

? Fast Word Program Time – 15 μs

? Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

? Low-power Operation

– 12 mA Active

– 13 μA Standby

? Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

? VPP Pin for Write Protection and Accelerated Program/Erase Operations

? RESET Input for Device Initialization

? Sector Lockdown Support

? Top or Bottom Boot Block Configuration Available

? 128-bit Protection Register

? Minimum 100,000 Erase Cycles

PSRAM

? 8-megabit (512K x 16)

? 2.7V to 3.3V VCC

? 70 ns Access Time

? Extended Temperature Range

? ISB0