1 Features

Processor cores:

? Dual- or quad-core Arm? Cortex?-A53

microprocessor subsystem at up to 1.1 GHz

– Up to two dual-core or two single-core Arm?

Cortex?-A53 clusters with 512KB L2 cache

including SECDED

– Each A53 core has 32KB L1 ICache and 32K

L1 DCache

? Dual-core Arm? Cortex?-R5F at up to 400 MHz

– Supports lockstep mode

– 16KB ICache, 16KB DCache, and 64KB RAM

per R5F core

Industrial subsystem:

? Three gigabit Industrial Communication

Subsystems (PRU_ICSSG)

– Up to two 10/100/1000 Ethernet ports per

PRU_ICSSG

– Supports two SGMII ports(2)

– Compatibility with 10/100Mb PRU-ICSS

– 24× PWMs per PRU_ICSSG

? Cycle-by-cycle control

? Enhanced trip control

– 18× Sigma-delta filters per PRU_ICSSG

? Short circuit logic

? Over-current logic

– 6× Multi-protocol position encoder interfaces

per PRU_ICSSG

Memory subsystem:

? Up to 2MB of on-chip L3 RAM with SECDED

? Multi-core Shared Memory Controller (MSMC)

– Up to 2MB (2 banks × 1MB) SRAM with

SECDED

? Shared coherent Level 2 or Level 3

memory-mapped SRAM

? Shared coherent Level 3 Cache

– 256-bit processor port bus and 40-bit physical

address bus

– Coherent unified bi-directional interfaces to

connect to processors or device masters

– L2, L3 Cache pre-warming and post flushing

– Bandwidth management with starvation bound

– One infrastructure master interface

– Single external memory master interface

– Supports distributed virtual system

– Supports internal DMA engine – Data Routing

Unit (DRU)

– ECC error protection

? DDR Subsystem (DDRSS)

– Supports DDR4 memory types up to DDR-1600

– 32-bit data bus and 7-bit SECDED bus

– 8 GB of total addressable space

? General-Purpose Memory Controller (GPMC)

SafeTI? semiconductor component:

? Designed for functional safety applications

? Developed according to the requirements of IEC

61508

? Achieves systematic integrity of SIL-3

? For the MCU safety island, sufficient diagnostics

are included to achieve random fault integrity

requirements of SIL-2

? For the rest of the SoC, sufficient diagnostics

are included to achieve random fault integrity

requirements of SIL-2

? In addition, sufficient architectural metrics are in

place to achieve execution of SIL-3 applications

given a proper safety concept (for example

reciprocal comparison by software)

? Functional safety manual available

? Safety-related certification

– Component level functional safety certification

by TüV SüD [certification in progress]

? Functional safety features:

– ECC or parity on calculation-critical memories

and internal bus interconnect

– Firewalls to help provide Freedom From

Interference (FFI)

? Built-In Self-Test (BIST) for CPU, high-end

timers, and on-chip RAM

– Hardware error injection support for test-fordiagnostics

– Error Signaling Modules (ESM) for capture of

functional safety related errors

– Voltage, temperature, and clock monitoring

– Windowed and non-windowed watchdog timers

in multiple clock domains

? MCU island

– Isolation of the dual-core Arm? Cortex?-R5F

microprocessor subsystem

– Separate voltage, clocks, resets, and dedicated

peripherals

– Internal MCSPI connection to the rest of SoC

Security:

? Secure boot supported

– Hardware-enforced root-of-trust

– Support to switch root-of-trust via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

? Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– Supports cryptographic cores

? AES – 128/192/256 bits key sizes

? 3DES – 56/112/168 bits key sizes

? MD5, SHA1

? SHA2 – 224/256/384/512

? DRBG with true random number generator

? PKA (public key accelerator) to assist in

RSA/ECC processing

– DMA support

? Debugging security

– Secure software-controlled debug access

– Security aware debugging

? Trusted Execution Environment (TEE) supported

– Arm? TrustZone? based TEE

– Extensive firewall support for isolation

– Secure DMA path and interconnect

– Secure watchdog/timer/IPC

? Secure storage support

? On-the-fly encryption and authentication support

for OSPI interface

? Networking security support for data (payload)

encryption/authentication via packet based

hardware cryptographic engine

? Security coprocessor (DMSC) for key and

security management, with dedicated device level

interconnect for security software

SoC services:

? Device Management Security Controller (DMSC)

– Centralized SoC system controller

– Manages system services including initial boot,

security, functional safety and clock/reset/power

management

– Power management controller for active and

low power modes

– Communication with various processing units

over message manager

– Simplified interface for optimizing unused

peripherals

– Tracing and debugging capability

? Sixteen 32-bit general-purpose timers

? Two data movement and control Navigator

Subsystems (NAVSS)

– Ring Accelerator (RA)

– Unified DMA (UDMA)

– Up to 2 Timer Managers (TM) (1024 timers

each)

Multimedia:

? Display subsystem

– Two fully input-mapped overlay managers

associated with two display outputs

– One port MIPI? DPI parallel interface

– One port OLDI

? PowerVR? SGX544-MP1 3D Graphics Processing

Unit (GPU)

? One Camera Serial Interface-2 (MIPI CSI-2)

? One port video capture: BT.656/1120 (no

embedded sync)

High-speed interfaces:

? One Gigabit Ethernet (CPSW) interface supporting

– RMII (10/100) or RGMII (10/100/1000)

– IEEE1588 (2008 Annex D, Annex E, Annex F)

with 802.1AS PTP

– Audio/video bridging (P802.1Qav/D6.0)

– Energy-efficient Ethernet (802.3az)

– Jumbo frames (2024 bytes)

– Clause 45 MDIO PHY management

? Two PCI-Express? ( PCIe?) revision 3.1

subsystems(2)

– Supports Gen2 (5.0GT/s) operation

– Two independent 1-lane, or a single 2-lane port

– Support for concurrent root-complex and endpoint

operation

? USB 3.1 Dual-Role Device (DRD) subsystem(2)

– One enhanced SuperSpeed Gen1 port

– One USB 2.0 port

– Each port independently configurable as USB

host, USB peripheral, or USB DRD

General connectivity:

? 6× Inter-Integrated Circuit ( I2C?) ports

? 5× configurable UART/IrDA/CIR modules

? Two simultaneous flash interfaces configured as

– Two OSPI flash interfaces

– or HyperBus? and OSPI1 flash interface

? 2× 12-bit Analog-to-Digital Converters (ADC)

– Up to 4 Msamples/s

– Eight multiplexed analog inputs

? 8× Multichannel Serial Peripheral Interfaces

(MCSPI) controllers

– Two with internal connections

– Six with external interfaces

? General-Purpose I/O (GPIO) pins

Control interfaces:

? 6× Enhanced High-Resolution Pulse-Width

Modulator (EHRPWM) modules

? One Enhanced Capture (ECAP) module

? 3× Enhanced Quadrature Encoder Pulse (EQEP)

modules

Automotive interfaces:

? 2× Modular Controller Area Network (MCAN)

modules with full CAN-FD support

Audio interfaces:

? 3× Multichannel Audio Serial Port (MCASP)

modules

Media and data storage:

? 2× Multimedia Card?/ Secure Digital? ( MMC?/

SD?) interfaces

Simplified power management:

? Simplified power sequence with full support for

dual voltage I/O

? Integrated LDOs reduces power solution

complexity

? Integrated SDIO LDO for handling automatic

voltage transition for SD interface

? Integrated Power On Reset (POR) generation

reducing power solution complexity

? Integrated voltage supervisor for functional safety

monitoring

? Integrated power supply glitch detector for

detecting fast power supply transients

Analog/system integration:

? Integrated USB VBUS detection

? Fail safe I/O for DDR RESET

? All I/O pins drivers disabled during reset to avoid

bus conflicts

? Default I/O pulls disabled during reset to avoid

system conflicts

? Support dynamic I/O pinmux configuration change

System-on-Chip (SoC) architecture:

? Supports primary boot from UART, I2C, OSPI,

HyperBus, parallel NOR Flash, SD or eMMC?,

USB, PCIe, and Ethernet interfaces

? 28-nm CMOS technology

? 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA

(ACD)

2 Applications

? Industrial Programmable Logic Controllers (PLC)

? Factory automation with safety functions

? Multi-protocol fieldbus communications

? Industrial PC

? Industrial robots

? Human Machine Interface (HMI)

? Grid infrastructure protection relays

? Robotic motor drives

3 Description

AM654x and AM652x Sitara? processors are Arm? applications processors built to meet the complex

processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm? Cortex?-A53 cores with a dual Arm? Cortex?-R5F

MCU subsystem which includes features intended to help customers achieve their functional safety goals for

their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC

capable of high-performance industrial controls with industrial connectivity and processing for functional safety

applications. AM65xx is currently undergoing assessment to be certified by TüV SüD according to IEC 61508.

The four Arm? Cortex?-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2

memory to create two processing channels. The two Arm? Cortex?-A53 cores in the AM652x are available

in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip

memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help

customers design systems that can achieve their functional safety goals (assessment pending with TüV SüD).

Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to

granular firewalls managed by the DMSC.

Programmability is provided by the Arm? Cortex?-A53 RISC CPUs with Arm? Neon? extension, and the dual

Arm? Cortex?-R5F MCU subsystem is available for general purpose use as two cores or it can be used in

lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to

provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT? (among many

others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm? cores including Processor SDK

Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into

source code execution. Applicable functional safety and security documentation will be made available to assist

customers in developing their functional safety or security related systems.