1 Features

Processor cores:

? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor

subsystem at up to 1.0 GHz

– Dual-core Cortex-A53 cluster with 256KB L2

shared cache with SECDED ECC

– Each A53 Core has 32KB L1 DCache with

SECDED ECC and 32KB L1 ICache with Parity

protection

? Up to 2× Dual-core Arm? Cortex?-R5F MCU

subsystems at at up to 800 MHz, integrated for

real-time processing

– Dual-core Arm? Cortex?-R5F supports dualcore

and single-core modes

– 32KB ICache, 32KB DCache and 64KB TCM

per each R5F core for a total of 256KB TCM

with SECDED ECC on all memories

? 1× Single-core Arm? Cortex?-M4F MCU at up to

400 MHz

– 256KB SRAM with SECDED ECC

Industrial subsystem:

? 2× gigabit Industrial Communication Subsystems

(PRU_ICSSG)

– Supports Profinet IRT, Profinet RT, EtherNet/IP,

EtherCAT, Time-Sensitive Networking (TSN),

and more

– Backward compatibility with 10/100Mb

PRU_ICSS

– Each PRU_ICSSG contains:

? 2× Ethernet ports

– MII (10/100)

– RGMII (10/100/1000)

? 6 PRU RISC cores per PRU_ICSSG each

core having:

– Instruction RAM with ECC

– Broadside RAM

– Multiplier with optional accumulator

(MAC)

– CRC16/32 hardware accelerator

– Byte swap for Big/Little Endian

conversion

– SUM32 hardware accelerator for UDP

checksum

– Task Manager for preemption support

? Three Data RAMs with ECC

? 8 banks of 30 × 32-bit register scratchpad

memory

? Interrupt controller and task manager

? Two 64-bit Industrial Ethernet Peripherals

(IEPs) for time stamping and other time

synchronization functions

? 18× Sigma-Delta filters

– Short circuit logic

– Over-current logic

? 6× Multi-protocol position encoder interfaces

? One Enhanced Capture Module (ECAP)

? 16550-compatible UART with a dedicated

192-MHz clock to support 12-Mbps

PROFIBUS

Memory subsystem:

? Up to 2MB of On-chip RAM (OCSRAM) with

SECDED ECC:

– Can be divided into smaller banks in

increments of 256KB for as many as 8 separate

memory banks

– Each memory bank can be allocated to a single

core to facilitate software task partitioning

? DDR Subsystem (DDRSS)

– Supports LPDDR4, DDR4 memory types

– 16-Bit data bus with inline ECC

– Supports speeds up to 1600 MT/s

? 1× General-Purpose Memory Controller (GPMC)

– 16-Bit parallel bus with 133 MHz clock or

– 32-Bit parallel bus with 100 MHz clock

– Error Location Module (ELM) support

System on Chip (SoC) Services:

? Device Management Security Controller (DMSC-L)

– Centralized SoC system controller

– Manages system services including initial boot,

security, and clock/reset/power management

– Communication with various processing units

over message manager

– Simplified interface for optimizing unused

peripherals

? Data Movement Subsystem (DMSS)

– Block Copy DMA (BCDMA)

– Packet DMA (PKTDMA)

– Secure Proxy (SEC_PROXY)

– Ring Accelerator (RINGACC)

Security:

? Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

? Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– Supports cryptographic cores

? AES – 128/192/256 Bits key sizes

? 3DES – 56/112/168 Bits key sizes

? MD5, SHA1

? SHA2 – 224/256/384/512

? DRBG with true random number generator

? PKA (Public Key Accelerator) to Assist in

RSA/ECC processing

– DMA support

? Debugging security

– Secure software controlled debug access

– Security aware debugging

? Trusted Execution Environment (TEE) supported

– Arm TrustZone? based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

? Secure storage support

? On-the-Fly encryption support for OSPI interface in

XIP mode

? Networking security support for data (Payload)

encryption/authentication via packet based

hardware cryptographic engine

? Security co-processor (DMSC-L) for key and

security management, with dedicated device level

interconnect for security

High-speed interfaces:

? 1× Integrated Ethernet switch (CPSW3G)

supporting

– Up to 2 Ethernet ports

? RMII (10/100)

? RGMII (10/100/1000)

– IEEE 1588 (2008 Annex D, Annex E, Annex F)

with 802.1AS PTP

– Clause 45 MDIO PHY management

– Energy efficient Ethernet (802.3az)

? 1× PCI-Express? Gen2 controller (PCIE)

– Supports Gen2 operation

– Supports Single Lane operation

? 1× USB 3.1-Gen1 Dual-Role Device (DRD)

Subsystem (USBSS)

– One enhanced SuperSpeed Gen1 port

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device

– Integrated USB VBUS detection

General connectivity:

? 6× Inter-Integrated Circuit (I2C) ports

? 9× configurable Universal Asynchronous Recieve/

Transmit (UART) modules

? 1× Flash Subsystem (FSS) that can be configured

as Octal SPI (OSPI) flash interfaces or one Quad

SPI (QSPI)

? 1× 12-Bit Analog-to-Digital Converters (ADC)

– Up to 4 MSPS

– 8× multiplexed analog inputs

? 7× Multichannel Serial Peripheral Interfaces

(MCSPI) controllers

? 6× Fast Serial Interface Receiver (FSI_RX) cores

? 2× Fast Serial Interface Transmitter (FSI_TX)

cores

? 3× General-Purpose I/O (GPIO) modules

Control interfaces:

? 9x Enhanced Pulse-Width Modulator (EPWM)

modules

? 3× Enhanced Capture (ECAP) modules

? 3× Enhanced Quadrature Encoder Pulse (EQEP)

modules

? 2× Modular Controller Area Network (MCAN)

modules with or without full CAN-FD support

Media and data storage:

? 2× Multi-Media Card/Secure Digital (MMC/SD/

SDIO) interfaces

– One 4-bit for SD/SDIO;

– One 8-bit for eMMC

– Integrated analog switch for voltage switching

between 3.3V to 1.8V for high-speed cards

Power management:

? Simplified power sequence

? Integrated SDIO LDO for handling automatic

voltage transition for SD interface

? Integrated voltage supervisor for safety monitoring

of over-under voltage conditions

? Integrated power supply glitch detector for

detecting fast supply transients

Functional Safety:

? Functional Safety-Compliant targeted

– Developed for functional safety applications

– Documentation will be available to aid IEC

61508 functional safety system design

– Systematic capability up to SIL 3

– Hardware integrity up to SIL 2 targeted for MCU

domain

– Quality-Managed Main Domain

– Safety-related certification

? IEC 61508 certification planned

– ECC or parity on calculation-critical memories

– ECC and parity on select internal bus

interconnect

– Built-In Self-Test (BIST) for CPU and on-chip

RAM

– Error Signaling Module (ESM) with error pin

– Runtime safety diagnostics, voltage,

temperature, and clock monitoring, windowed

watchdog timers, CRC engine for memory

integrity checks

– Dedicated MCU domain memory, interfaces,

and M4F core capable of being isolated from

the larger SoC with Freedom From Interference

(FFI) features

? Separate interconnect

? Firewalls and timeout gaskets

? Dedicated PLL

? Dedicated I/O supply

? Separate reset

SoC architecture:

? Supports primary boot from UART, I2C, OSPI/

QSPI Flash, SPI Flash, parallel NOR Flash,

parallel NAND Flash, SD, eMMC, USB 2.0, PCIe,

and Ethernet interfaces

? 16-nm FinFET technology

? 17.2 mm × 17.2 mm, 0.8-mm pitch, 441-pin BGA

package

2 Applications

? Programmable Logic Controller (PLC)

? Motor Drives

? Remote I/O

? Industrial Robots

3 Description

AM64x is an extension of the Sitara? Industrial-grade family of heterogeneous Arm? processors. AM64x is built

for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a

unique combination of real-time processing and communications with applications processing. AM64x combines

two instances of the Sitara device's gigabit TSN-enabled PRU-ICSSG with up to two Arm? Cortex?-A53 cores,

up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled

Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for

rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight

control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters,

and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Realtime

(RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term

Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux

world with the real-time world by enabling isolation between Linux applications and real-time streams through

configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and

the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT

slave, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability

for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC

including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with its dedicated

peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.