AHA4011C中文資料ETC數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

[Advanced Hardware Architectures, Inc.]

INTRODUCTION

The AHA4011C is a single chip integrated circuit that implements a high speed Reed-Solomon Forward Error Correction algorithm. The AHA4011C is a member of the AHA PerFEC? family of high speed forward error correction (FEC) devices conforming to the Intelsat IESS-308 specification.

FEATURES

HIGH PERFORMANCE

? Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) standards

? 40 MBytes/sec burst transfer rate with a 40 MHz clock for all block lengths

? Maximum channel rate of 10 MBytes/sec continuous for block lengths from 54 bytes through 255 bytes using a 40 MHz clock

? Processing latency time less than 15.2 μsec in continuous operation for block lengths of 100 bytes

FLEXIBILITY

? Programmable to correct from 1 to 10 error bytes or 20 erasure bytes per block

? Block lengths programmable from 3 to 255 bytes

? Encode, decode or pass-through capability inline with data flow

? Outputs corrected data or correction vectors in forward or reverse order

? Continuous or burst data transfer

? Programmable error threshold to help determine channel performance

SYSTEM INTERFACE

? Byte wide synchronous I/O ports with internal buffering on both ports

? Dedicated control pins permit discontinuities in system data flow

OTHERS

? 44 pin PLCC; 50 mil lead pitch

? Pin and plug compatible with lower performance AHA4012B

? Software emulation of the algorithm available