AFE2256TDU集成電路（IC）的模擬前端（AFE）規(guī)格書PDF中文資料

AFE2256TDU屬于集成電路（IC）的模擬前端（AFE）。由德州儀器制造生產(chǎn)的AFE2256TDU模擬前端（AFE）模擬前端 (AFE) 是一種用于信號(hào)調(diào)節(jié)的半導(dǎo)體器件，由模擬放大器、運(yùn)算放大器、濾波器和集成電路構(gòu)成。這種可配置功能塊能連接各種傳感器。分辨率范圍從 8 位至 42 位不等，通道數(shù)范圍為 1 至 256 個(gè)。

1 Features

? 256 Channels

? On-Chip, 16-Bit ADC

? Photodiode Short Immunity

? High Performance:

– Noise: 750 Electrons RMS

(1.2-pC Input Charge Range)

– Low Correlated Noise

– Integral Nonlinearity:

±2 LSB with Internal 16-Bit ADC

– Scan Time: < 20 μs to 204.8 μs

? Integration:

– Six Selectable, Full-Scale Input Ranges:

0.6 pC (Minimum) to 9.6 pC (Maximum)

– Internal Timing Generator (TG)

– Built-In Correlated Double Sampler

– Pipelined Integrate-and-Read for Improved

Throughput—Data-Read During Integration

– Serial LVDS Output

? Simple Power-Supply Scheme:

– AVDD1 = 1.85 V

– AVDD2 = 3.3 V

? Low Power Consumption

? Nap and Total Power-Down Modes

? Custom Chip-On-Film (COF) Packages

2 Applications

? Flat-Panel, X-Ray Detectors

? Charge Detectors

? Capacitance Measurement

3 Description

The AFE2256 is a 256-channel, analog front-end

(AFE) designed to suit the requirements of flat-panel

detector (FPD) based digital x-ray systems. The

device includes 256 integrators, a programmable gain

amplifier (PGA) for full-scale charge level selection,

a correlated double sampler with dual banking, and

256:4 analog multiplexers.

The device also features four 16-bit successiveapproximation

register (SAR) analog-to-digital

converters (ADCs). Serial data from the ADCs are

available in low-voltage differential signaling (LVDS)

format.

The nap and power-down modes enable substantial

power savings, and are especially useful in batterypowered

systems.

To request a full datasheet or other design resources:

request AFE2256