ADSP-BF524集成電路（IC）的DSP（數(shù)字信號(hào)處理器）規(guī)格書(shū)PDF中文資料

ADSP-BF524屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-BF524DSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-BF52x processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin? processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Specifications on Page 28

Programmable on-chip voltage regulator (ADSP-BF523/

ADSP-BF525/ADSP-BF527 processors only)

Qualified for Automotive Applications. See Automotive

Products on Page 87

289-ball and 208-ball CSP_BGA packages

MEMORY

132K bytes of on-chip memory (See Table 1 on Page 3 for L1

and L3 memory size details)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI, and TWI

memory or from host devices including SPI, TWI, and UART

Code security with Lockbox Secure Technology

one-time-programmable (OTP) memory

Memory management unit providing memory protection

PERIPHERALS

USB 2.0 high speed on-the-go (OTG) with integrated PHY

IEEE 802.3-compliant 10/100 Ethernet MAC

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

Host DMA port (HOSTDP)

2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I2S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

2 memory-to-memory DMAs with external request lines

Event handler with 54 interrupt inputs

Serial peripheral interface (SPI) compatible port

2 UARTs with IrDA support

2-wire interface (TWI) controller

Eight 32-bit timers/counters with PWM support

32-bit up/down counter with rotary support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), with programmable

hysteresis

NAND flash controller (NFC)

Debug/JTAG interface

On-chip PLL capable of frequency multiplication