ADSP-2104集成電路（IC）的DSP（數(shù)字信號處理器）規(guī)格書PDF中文資料

ADSP-2104屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的ADSP-2104DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運算為主的算法，而不是以條件邏輯或大量并發(fā)進程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-2104 and ADSP-2109 processors are single-chip microcomputers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2104/ADSP-2109 processors are built upon a common core. Each processor combines the core DSP architecture— computation units, data address generators, and program sequencer—with differentiating features such as on-chip program and data memory RAM (ADSP-2109 contains 4K words of program ROM), a programmable timer, and two serial ports.

SUMMARY

16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory

Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses

Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter

Single-Cycle Instruction Execution & Multifunction Instructions

On-Chip Program Memory RAM or ROM & Data Memory RAM

Integrated I/O Peripherals: Serial Ports and Timer

FEATURES

20 MIPS, 50 ns Maximum Instruction Rate

Separate On-Chip Buses for Program and Data Memory

Program Memory Stores Both Instructions and Data (Three-Bus Performance)

Dual Data Address Generators with Modulo and Bit-Reverse Addressing

Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup

Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM )

Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation

Three Edge- or Level-Sensitive Interrupts

Low Power IDLE Instruction

PLCC Package