ADN8102-EVALZ中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

FEATURES

Optimized for dc to 3.75 Gbps data

Programmable input equalization

Up to 22 dB boost at 1.875 GHz

Compensates up to 30 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Programmable output pre-emphasis/de-emphasis

Up to 12 dB boost at 1.875 GHz (3.75 Gbps)

Compensates up to 15 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Flexible 1.8 V to 3.3 V core supply

Per lane P/N pair inversion for routing ease

Low power: 125 mW/channel up to 3.75 Gbps

DC- or ac-coupled differential CML inputs

Programmable CML output levels

50 Ω on-chip termination

Loss-of-signal detection

Temperature range operation: ?40°C to +85°C

Supports 8b10b, scrambled, or uncoded NRZ data

I2C control interface

64-lead LFCSP (QFN) package

APPLICATIONS

10GBase-CX4

HiGig?

InfiniBand?

1×, 2× Fibre Channel

XAUI?

Gigabit Ethernet over backplane or cable

CPRI?

50 Ω cables