ADF4154BCP集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

ADF4154BCP屬于集成電路（IC）的時鐘發(fā)生器PLL頻率合成器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADF4154BCP時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

GENERAL DESCRIPTION

The ADF4154 is a fractional-N frequency synthesizer that implements local oscillators in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N-divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R-counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage-controlled oscillator (VCO).

FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate VP allows extended tuning voltage

Programmable dual-modulus prescaler 4/5, 8/9

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the ADF4110/ADF4111/ADF4112/ADF4113, ADF4106, ADF4153

Programmable modulus on fractional-N synthesizer

Trade-off noise vs. spurious performance

Fast-lock mode with built-in timer

Loop filter design possible with ADIsimPLL?