ADF4111集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

ADF4111屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADF4111時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號(hào)的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動(dòng)器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N

division. The INT, FRAC, and MOD registers define an overall N divider (N= (INT+ (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).

FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate VP allows extended tuning voltage

Y version available: ?40°C to +125°C

Programmable fractional modulus

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113

and ADF4106

Consistent RF output phase

Loop filter design possible with ADIsimPLL

Qualified for automotive applications

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)

Wireless LANs, PMR

Communications test equipment