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ADC3664-SP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
廠商型號(hào) |
ADC3664-SP |
功能描述 | ADC3664-SP Radiation-Hardness-Assured 14-Bit, Dual Channel, 1 to 125MSPS, Low Latency, Low Noise, Ultra-low Power, Analog-to-Digital Converter (ADC) |
文件大小 |
2.32553 Mbytes |
頁(yè)面數(shù)量 |
66 頁(yè) |
生產(chǎn)廠商 | Texas Instruments |
企業(yè)簡(jiǎn)稱 |
TI【德州儀器】 |
中文名稱 | 美國(guó)德州儀器公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-1-16 11:45:00 |
ADC3664-SP規(guī)格書(shū)詳情
1 Features
? Screening and radiation performance
– QMLV screening and reliability assurance
– Total ionizing dose (TID): 300krad (Si)
– Single event latch-up (SEL): 75MeV-cm2/mg
? Ambient temperature range: -55°C to 105°C
? Dual Channel ADC
? 14-bit 125MSPS
? Noise floor: -156.9dBFS/Hz
? Low power consumption: 100mW/ch
? Latency: 2 clock cycles
? Clock rate versus voltage reference:
– External reference: 1MSPS to 125MSPS
– Internal reference: 100MSPS to 125MSPS
? 14-Bit, no missing codes
? Input bandwidth: 200MHz (-3dB)
? INL: ±2.6LSB; DNL: ±0.9LSB
? Optional digital down converter (DDC):
– Real or complex decimation
– Decimation by 2, 4, 8, 16, and 32
– 32-bit NCO
? Serial LVDS (SLVDS) interface (2-, 1-, and
1/2-wire)
? Spectral performance (FIN = 5MHz):
– SNR: 77.5dBFS
– SFDR: 84dBc HD2, HD3
– Non HD23: 91dBc
2 Applications
? Optical imaging payload
? Radar imaging payload
? Satellite communication payloads
3 Description
The ADC3664-SP is a low latency, low noise, and
ultra low power, 14-bit, 125MSPS, high-speed dual
channel ADC. Designed for best noise performance,
the device delivers a noise spectral density of –
156.9dBFS/Hz combined with excellent linearity and
dynamic range. The ADC3664-SP offers DC precision
together with IF sampling support to enable the
design of a wide range of applications. The low
latency architecture (as low as 1 clock cycle latency)
and high sample rate also enable high speed
control loops. The ADC consumes only 100mW/ch
at 125MSPS and the power consumption scales well
with sampling rate.
The device uses a serial LVDS (SLVDS) interface to
output the data which minimizes the number of digital
interconnects. The device also integrates a digital
down converter (DDC) to help reduce the data rate
and lower system power consumption. The device
is pin-to-pin compatible with the 18-bit, 65MSPS
ADC3683-SP. It comes in a 64-pin CFP package
(10.9mm x 10.9mm) and supports a temperature
range from –55°C to +105°C.
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TI/德州儀器 |
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NS |
23+ |
DIP24 |
1350 |
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詢價(jià) | ||
NS/國(guó)半 |
2021+ |
DIP24 |
100500 |
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