AD9865BCPZRLRF/IF射頻/中頻RFID的射頻前端（LNA+PA）規(guī)格書PDF中文資料

AD9865BCPZRL屬于RF/IF射頻/中頻RFID的射頻前端（LNA+PA）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9865BCPZRL射頻前端（LNA + PA）本系列中的產(chǎn)品是各種集成電路，其中集成了射頻 (RF) 信號(hào)鏈連接到系統(tǒng)天線的部分中常見的一種或多種功能，如低噪聲放大器 (LNA) 和可編程放大器 (PA)。任何給定器件所含的實(shí)際功能各不相同，相比旨在提供更高應(yīng)用靈活性的器件，針對(duì)相對(duì)較窄應(yīng)用的器件通常集成更大一部分必要的信號(hào)鏈。

GENERAL DESCRIPTION

The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus

often allowing the AD9865 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks, or to power down unused blocks in half-duplex applications.

FEATURES

Low cost 3.3 V CMOS MxFETM for broadband modems

10-bit D/A converter

2×/4× interpolation filter

200 MSPS DAC update rate

Integrated 23 dBm line driver with 19.5 dB gain control

10-bit, 80 MSPS A/D converter

?12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz)

Third order, programmable low-pass filter

Flexible digital data path interface

Half- and full-duplex operation

Backward-compatible with AD9975 and AD9875

Various power-down/reduction modes

Internal clock multiplier (PLL)

2 auxiliary programmable clock outputs

Available in 64-lead chip scale package or bare die

APPLICATIONS

Powerline networking

VDSL and HPNA