AD9774ASZ集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9774ASZ屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9774ASZ數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字數(shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

PRODUCT DESCRIPTION

The AD9774 is a single supply, oversampling, 14-bit digital-to analog converter (DAC) optimized for waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 4×digital interpolation filter and clock multiplier. The two-stage, 4×digital interpolation filter provides more than a six-fold reduction in the complexity of the analog reconstruction-filter. It does so by multiplying the input data rate by a factor of four while simultaneously suppressing the original inband images by more than 69 dB. The on-chip clock multiplier provides all the necessary clocks. The AD9774 can reconstruct full-scale waveforms having bandwidths as high as 13.5 MHz when operating at an input data rate of 32 MSPS and a DAC output rate of 128 MSPS. The 14-bit DAC provides differential current outputs to support differential or single-ended applications. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The differential current outputs may be fed into a transformer or tied directly to an output resistor to provide two complementary, single-ended voltage outputs. A differential op amp topology can

also be used to obtain a single-ended output voltage. The output voltage compliance range is nominally 1.25 V.

FEATURES

Single 3 V or 5 V Supply

14-Bit DAC Resolution and Input Data Width

32 MSPS Input Data Rate at 5 V

13.5 MHz Reconstruction Bandwidth

12 ENOBS @ 1 MHz

77 dBc SFDR @ 5 MHz

43Interpolation Filter

69 dB Image Rejection

84 Passband to Nyquist Ratio

0.002 dB Passband Ripple

23 3/4 Cycle Latency

Internal 43Clock Multiplier

On-Chip 1.20 V Reference

44-Lead MQFP Package

APPLICATIONS

Communication Transmit Channel:

Wireless Basestations

ADSL/HFC Modems

Direct Digital Synthesis (DDS)