AD9571集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

AD9571屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9571時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號(hào)的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動(dòng)器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

GENERAL DESCRIPTION

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES

Fully integrated VCO/PLL core

0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz

Input crystal or clock frequency of 25 MHz

Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and

125 MHz

Choice of LVPECL or LVDS output format

Integrated loop filter

6 copies of reference clock output

Rates configured via strapping pins

Space saving 6 mm × 6 mm 40-lead LFCSP

0.48 W power dissipation (LVDS operation)

0.69 W power dissipation (LVPECL operation)

3.3 V operation

APPLICATIONS

Ethernet line cards, switches, and routers

SCSI, SATA, and PCI-express

PCI support included

Low jitter, low phase noise clock generation