AD9361RF/IF射頻/中頻RFID的射頻收發(fā)器IC規(guī)格書PDF中文資料

AD9361屬于RF/IF射頻/中頻RFID的射頻收發(fā)器IC。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9361射頻收發(fā)器 IC射頻收發(fā)器 IC 是將發(fā)射器和接收器集成于單個封裝的半導(dǎo)體器件。收發(fā)器適用于各種射頻系列產(chǎn)品或標(biāo)準(zhǔn)，例如 AISG、藍(lán)牙、ISM、VHF、Wi-Fi、蜂窩、雷達(dá)、802.15.4 和 Z-Wave。此產(chǎn)品可根據(jù)調(diào)制類型和特定協(xié)議版本進(jìn)一步分類。部分 IC 包含內(nèi)置微控制器。

GENERAL DESCRIPTION

The AD9361 is a high performance, highly integrated radio

frequency (RF) Agile Transceiver? designed for use in 3G and

4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.

The device combines a RF front end with a flexible mixed-signal

baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a

processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz

range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported. The two independent direct conversion receivers have state-of-the-

art noise figure and linearity. Each receive (RX) subsystem includes

independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating

the need for these functions in the digital baseband. The AD9361

also has flexible manual gain modes that can be externally

controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass

them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate. The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM)

of

power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements. The fully integrated phase-locked loops (PLLs) provide low

power fractional-N frequency synthesis for all receive and

transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design.

All VCO and loop filter components are integrated. The core of the AD9361 can be powered directly from a 1.3 V

regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive

power-down modes are included to minimize power consumption

during normal use. The AD9361 is packaged in a 10 mm × 10 mm,

144-ball chip scale package ball grid array (CSP_BGA).

FEATURES

RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs TX band: 47 MHz to 6.0 GHz RX band: 70 MHz to 6.0 GHz Supports TDD and FDD operation

Tunable channel bandwidth: <200 kHz to 56 MHz Dual receivers: 6 differential or 12 single-ended inputs Superior receiver sensitivity with a noise figure of 2 dB at

800 MHz LO RX gain control Real-time monitor and control signals for manual gain Independent automatic gain control Dual transmitters: 4 differential outputs Highly linear broadband transmitter TX EVM: ≤?40 dB

TX noise: ≤?157 dBm/Hz noise floor

TX monitor: ≥66 dB dynamic range with 1 dB accuracy Integrated fractional-N synthesizers 2.4 Hz maximum local oscillator (LO) step size

Multichip synchronization CMOS/LVDS digital interface

APPLICATIONS

Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems