AD9171開(kāi)發(fā)板套件編程器的評(píng)估板-數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書(shū)PDF中文資料

AD9171屬于開(kāi)發(fā)板套件編程器的評(píng)估板-數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9171評(píng)估板 - 數(shù)模轉(zhuǎn)換器（DAC）該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過(guò)驗(yàn)證的設(shè)計(jì)環(huán)境中對(duì)用于將數(shù)字?jǐn)?shù)據(jù)轉(zhuǎn)換為模擬格式的器件進(jìn)行性能或特性評(píng)估。重點(diǎn)器件涵蓋范圍從以適合學(xué)生或愛(ài)好者使用的方式實(shí)現(xiàn)的適度功能器件，到適合電信基礎(chǔ)設(shè)施應(yīng)用的高級(jí)器件。

FEATURES

? Supports single-band wireless applications

? 1 complex data input channel per RF DAC

? 516 MSPS maximum complex input data rate per input channel

? 1 independent NCO per input channel

? Proprietary, low spurious and distortion design

? 2-tone IMD = ?83 dBc at 1.8 GHz, ?7 dBFS/tone RF output

? SFDR < ?80 dBc at 1.8 GHz, ?7 dBFS RF output

? Flexible 8-lane, 15.4 Gbps JESD204B interface

? Supports single-band use cases

? Supports 12-bit high density mode for increased data throughput

? Multiple chip synchronization

? Supports JESD204B Subclass 1

? Selectable interpolation filter for a complete set of input data

rates

? 2×, 3×, 4×, and 6× configurable data channel interpolation

? 6× and 8× configurable final interpolation

? Final 48-bit NCO that operates at the DAC rate to support

frequency synthesis up to 3.1 GHz

? Transmit enable function allows extra power saving and downstream

circuitry protection

? High performance, low noise PLL clock multiplier

? Supports 6.2 GSPS DAC update rate

? Observation ADC clock driver with selectable divide ratios

? Low power

? 1.45 W at 6 GSPS, single-channel mode

? 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal

lid, 0.80 mm pitch

APPLICATIONS

? Wireless communications infrastructure

? Single-band base station radios

? Instrumentation, automatic test equipment (ATE)