AD9142ABCPZRL集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9142ABCPZRL屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9142ABCPZRL數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號(hào)轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機(jī)，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號(hào)，再連接到屏幕驅(qū)動(dòng)器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.

FEATURES

Supports input data rate up to 575 MHz

Very small inherent latency variation: <2 DAC clock cycles

Proprietary low spurious and distortion design

6-carrier GSM ACLR = 79 dBc at 200 MHz IF

SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF

Flexible 16-bit LVDS interface

Supports word and byte load

Data interface DLL

Sample error detection and parity

Multiple chip synchronization

Fixed latency and data generator latency compensation

Selectable 2×, 4×, 8× interpolation filter

Low power architecture

fS/4 power saving coarse mixer

Input signal power detection

Emergency stop for downstream analog circuitry

protection

FIFO error detection

On-chip numeric control oscillator allows carrier placement

anywhere in the DAC Nyquist bandwidth

Transmit enable function for extra power saving

High performance, low noise PLL clock multiplier

Digital gain and phase adjustment for sideband suppression

Digital inverse sinc filter

Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full

operating conditions

72-lead LFCSP

APPLICATIONS

Wireless communications: 3G/4G and MC-GSM base stations,

wideband repeaters, software defined radios

Wideband communications: point-to-point, LMDS/MMDS

Transmit diversity/MIMO

Instrumentation

Automated test equipment