AD6654BBC集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD6654BBC屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術有限公司制造生產(chǎn)的AD6654BBC模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD6654 is a mixed-signal IF-to-baseband receiver consisting of a 14-bit, 92.16 MSPS analog-to-digital converter (ADC) and a 4-/6-channel, multimode digital down-converter (DDC) capable of processing up to six WCDMA (wideband code division multiple access) channels. The AD6654 has been optimized for the demanding filtering requirements of wideband standards such as CDMA2000, UMTS, and TD-SCDMA, but is flexible enough to support wider standards such as WiMAX. It is typically used as part of a radio system that digitally demodulates and filters IF sampled signals.

FEATURES

SNR = 90 dB in 1.25 MHz bandwidth to Nyquist

SNR = 87 dB in 1.25 MHz bandwidth to 200 MHz

Integrated 14-bit, 92.16 MSPS ADC

IF sampling frequencies to 200 MHz

Internal 2.4 V reference, 2.2 V p-p analog input range

Internal differential track-and-hold analog input

Processes 4/6 wideband carriers simultaneously

Fractional clock multiplier to 200 MHz

Programmable decimating FIR filters, interpolating

half-band filters and programmable AGC loops

with 96 dB range

Three 16-bit configurable parallel output ports

User-configurable built-in self-test (BIST) capability

8-/16-bit microport and SPORT/SPI? serial port control

APPLICATIONS

Multicarrier, multimode digital receivers

GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000,

TD-SCDMA, WiMAX

Micro and pico cell systems, software radios

Wireless local loop

Smart antenna systems

In-building wireless telephony

Broadband data applications

Instrumentation and test equipment