AD532JDZ集成電路（IC）的模擬乘法器、除法器規(guī)格書PDF中文資料

AD532JDZ屬于集成電路（IC）的模擬乘法器、除法器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD532JDZ模擬乘法器、除法器模擬乘法器獲取兩個或更多模擬信號，并產(chǎn)生這些信號的乘積或乘積之和的輸出。此類電路可用于實現(xiàn)相關(guān)計算功能，例如計算平方（對兩個輸入都施加相同的信號）和平方根。應(yīng)用可能包括可變增益放大器、環(huán)形調(diào)制器、乘積檢測器、混頻器、增益控制、真 RMS 轉(zhuǎn)換器和脈沖幅度調(diào)制器 (PAM)。

GENERAL DESCRIPTION

The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of ±1.0 and a ±10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks.

FEATURES

Pretrimmed to ±1.0 (AD532K)

No external components required

Guaranteed ±1.0 maximum 4-quadrant error (AD532K)

Differential Inputs for (X1 ? X2) (Y1 ? Y2)/10 V transfer function

Monolithic construction, low cost

APPLICATIONS

Multiplication, division, squaring, square rooting

Algebraic computation

Power measurements

Instrumentation applications

Available in chip form