GENERAL DESCRIPTION

The AD4630-24/AD4632-24 are two-channel, simultaneous sampling,

Easy Drive?, 2 MSPS or 500 kSPS successive approximation

register (SAR) analog-to-digital converters (ADCs). With a

guaranteed maximum ±0.9 ppm INL and no missing codes at

24 bits, the AD4630-24/AD4632-24 achieve unparalleled precision

from ?40°C to +125°C. Figure 1 shows the functional architecture of

the AD4630-24/AD4632-24.

A low drift, internal precision reference buffer eases voltage

reference sharing with other system circuitry. The AD4630-24/

AD4632-24 offer a typical dynamic range of 106 dB when using

a 5 V reference. The low noise floor enables signal chains requiring

less gain and lower power. A block averaging filter with programmable

decimation ratio can increase dynamic range up to 153 dB.

The wide differential input and common-mode ranges allow inputs

to use the full voltage reference (±VREF) range without saturating,

simplifying signal conditioning requirements and system calibration.

The improved settling of the Easy Drive analog inputs broadens

the selection of analog front-end components compatible with the

AD4630-24/AD4632-24. Both single-ended and differential signals

are supported.

The versatile Flexi-SPI serial peripheral interface (SPI) eases host

processor and ADC integration. A wide data clocking window, multiple

SDO lanes, and optional dual data rate (DDR) data clocking can

reduce the serial clock to 10 MHz while operating at a sample rate

of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock

mode relax the timing requirements and simplify the use of digital

isolators.

The 64-ball chip scale package ball grid array (CSP_BGA) of

the AD4630-24/AD4632-24 integrates all critical power supply and

reference bypass capacitors, reducing the footprint and system

component count, and lessening sensitivity to board layout.

FEATURES

? High performance

? Throughput: 2 MSPS (AD4630-24) or 500 kSPS (AD4632-24)

per channel maximum

? INL: ±0.9 ppm maximum from ?40°C to +125°C

? SNR: 105.7 dB typical

? THD: ?127 dB typical

? NSD: ?166 dBFS/Hz typical

? Low power

? 15 mW per channel at 2 MSPS

? 5 mW per channel at 500 kSPS

? 1.5 mW per channel at 10 kSPS

? Easy Drive features reduce system complexity

? Low 0.6 μA input current for dc inputs at 2 MSPS

? Wide input common-mode range: ?(1/128) × VREF to

+(129/128) × VREF

? Flexible external reference voltage range: 4.096 V to 5 V

? Accurate integrated reference buffer with 2 μF bypass

capacitor

? Programmable block averaging filter with up to 216 decimation

? Extended sample resolution to 30 bits

? Overrange and synchronization bits

? Flexi-SPI digital interface

? 1, 2, or 4 SDO lanes per channel allows slower SCK

? Echo clock mode simplifies use of digital isolator

? Compatible with 1.2 V to 1.8 V logic

? 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply

and reference capacitors to help reduce system footprint

APPLICATIONS

? Automatic test equipment

? Digital control loops

? Medical instrumentation

? Seismology

? Semiconductor manufacturing

? Scientific instrumentation

AD4632-24屬于集成電路（IC） > 模數(shù)轉換器（ADC）。亞德諾半導體技術有限公司制造生產(chǎn)的AD4632-24模數(shù)轉換器（ADC）模數(shù)轉換器（ADC、A/D 或 A 轉 D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉換器數(shù)和架構（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。