AD1555APRL集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD1555APRL屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD1555APRL模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD1555 is a complete sigma-delta modulator, combined with a programmable gain amplifier intended for low frequency,high dynamic range measurement applications. The AD1555 outputs a ones-density bitstream proportional to the analog input. When used in conjunction with the AD1556 digital filter/ decimator, a high performance ADC is realized.

FEATURES

AD1555

Fourth Order Σ-Δ Modulator

Large Dynamic Range

116 dB Min, 120 dB Typical @ 1 ms

117 dB Typical @ 0.5 ms

Low Input Noise: 80 nV rms @ 4 ms with

Gain of 34,128

Low Distortion: –111 dB Max, –120 dB Typical

Low Intermodulation: 122 dB

Sampling Rate at 256 kSPS

Very High Jitter Tolerance

No External Antialias Filter Required

Programmable Gain Front End

Input Range: ±2.25 V

Robust Inputs

Gain Settings: 1, 2.5, 8.5, 34, 128

Common-Mode Rejection (DC to 1 kHz)

93 dB Min, 101 dB Typical @ Gain of 1

77 mW Typical Low Power Dissipation

Standby Modes

AD1556

FIR Digital Filter/Decimator

Serial or Parallel Selection of Configuration

Output Word Rates: 250 SPS to 16 kSPS

6.2 mW Typ Low Power Dissipation

70 mW in Standby Mode

Reference Design and Evaluation Board with

Software Available

APPLICATIONS

Seismic Data Acquisition Systems

Chromatography

Automatic Test Equipment