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AD14160L中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書

AD14160L
廠商型號(hào)

AD14160L

功能描述

Quad-SHARC DSP Multiprocessor Family

文件大小

1.19367 Mbytes

頁面數(shù)量

52

生產(chǎn)廠商 Analog Devices
企業(yè)簡(jiǎn)稱

AD亞德諾

中文名稱

亞德諾半導(dǎo)體技術(shù)有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-10-26 11:10:00

AD14160L規(guī)格書詳情

GENERAL DESCRIPTION

The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array (CBGA) puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned out, beyond that from the CQFP package. The core of the multiprocessor is the ADSP-21060 DSP microcomputer. The AD14x60 modules have the highest performance—density and lowest cost— performance ratios of any in their class. They are ideal for applications requiring higher levels of performance and/or functionality per unit area.

PERFORMANCE FEATURES

ADSP-21060 Core Processor (. . . 34)

480 MFLOPS Peak, 320 MFLOPS Sustained

25 ns Instruction Rate, Single-Cycle Instruction Execution–Each of Four Processors

16 Mbit Shared SRAM (Internal to SHARCs)

4 Gigawords Addressable Off-Module Memory

Sixteen 40 Mbyte/s Link Ports (Four per SHARC)

Eight 40 Mbit/s Independent Serial Ports (Two from Each SHARC)

5 V and 3.3 V Operation

32-Bit Single Precision and 40-Bit Extended Precision IEEE Floating Point Data Formats, or 32-Bit Fixed Point Data Format

IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation

PACKAGING FEATURES

452-Lead Ceramic Ball Grid Array (CBGA)

1.85 (47 mm) Body Size

0.200 Max Height

0.050 Ball Pitch

29 Grams (typical)

θJC = 0.368°C/W

產(chǎn)品屬性

  • 型號(hào):

    AD14160L

  • 制造商:

    AD

  • 制造商全稱:

    Analog Devices

  • 功能描述:

    Quad-SHARC DSP Multiprocessor Family

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