ACS8525AP中文資料SEMTECH數(shù)據(jù)手冊PDF規(guī)格書

Description

The ACS8525A is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source,

for Line Cards in a SONET or SDH Network Element. The ACS8525A has fast activity monitors on the SEC clock

inputs and will implement automatic system protection switching against the Master clock failure. The selection

of the Master/Slave input can be forced by a Force Fast Switch pin. If both the Master and Slave input clocks fail, the Stand-by “Group” is selected or, if no Stand-by is available, the device enters Digital Holdover mode.

Features

◆? SONET/SDH applications up to OC-3/STM-1 bit rate.

?◆ Switches between grouped inputs (SEC/Sync pairs).

?◆ Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz multiples up to 155.52 MHz), plus Frame Sync/Multi Frame Sync.

?◆ Outputs: two SEC clocks at any of several spot frequencies from 2 kHz up to 77.76 MHz via the TTL/CMOS port and up to 311.04 MHz via the PECL/LVDS port.

?◆ Selectable clock I/O port technologies.

◆? Modes for E3/DS3 and multiple E1/DS1 rate output clocks.

?◆ Frequency translation of SEC input clock to a different local line card clock.

?◆ Robust input clock source activity monitoring on all inputs.

?◆ Supports Free-run, Locked and Digital Holdover modes of operation.

?◆ Automatic “Hit-less” source switchover on loss of input.

?◆ External force fast switch between SEC1/SEC2 inputs.

?◆ Phase Build-out for output clock phase continuity during input switchover.

?◆ PLL “Locked” and “Acquisition” bandwidths individually selectable from 18, 35 or 70 Hz.

?◆ Serial interface for device set-up.

?◆ Single 3.3 V operation.

?◆ Operating temperature (ambient) of 0 to +70°C.

?◆ Available in LQFP 64 package.

?◆ Lead (Pb)-free version available (ACS8525T), RoHS and WEEE compliant.