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ACS630D中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

ACS630D
廠商型號

ACS630D

功能描述

Radiation Hardened EDAC (Error Detection and Correction Circuit)

文件大小

489.72 Kbytes

頁面數(shù)量

4

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-3-4 8:30:00

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ACS630D規(guī)格書詳情

Description

The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected.

Features

? Devices QML Qualified in Accordance with MIL-PRF-38535

? Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil’ QM Plan

? 1.25 Micron Radiation Hardened SOS CMOS

? Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

? Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

? SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

? Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

? Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C

? Significant Power Reduction Compared to ALSTTL Logic

? DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 30 of VCC Max

??? - VIH = 70 of VCC Min

? Input Current ≤ 1μA at VOL, VOH

? Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)

產(chǎn)品屬性

  • 型號:

    ACS630D

  • 制造商:

    INTERSIL

  • 制造商全稱:

    Intersil Corporation

  • 功能描述:

    Radiation Hardened EDAC(Error Detection and Correction Circuit)

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