ACS373DMSR中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

? 1.25 Micron Radiation Hardened SOS CMOS

? Total Dose 300K RAD (Si)

? Single Event Upset (SEU) Immunity

<1 x 10-10 Errors/Bit-Day (Typ)

? SEU LET Threshold >80 MEV-cm2/mg

? Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range: -55oC to +125oC

? Significant Power Reduction Compared to ALSTTL Logic

? DC Operating Voltage Range: 4.5V to 5.5V

? Input Logic Levels

- VIL = 30 of VCC Max

- VIH = 70 of VCC Min

? Input Current ?1?A at VOL, VOH

Description

The Intersil ACS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent

to the inputs when the latch enable (LE) is high. When the LE

goes low, the data is latched. When the Output Enable (OE) is

high, the outputs are in the high impedance state. The latch

operation is independent of the state of the output enable.

The ACS373MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family