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ACS109D中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書

ACS109D
廠商型號(hào)

ACS109D

功能描述

Radiation Hardened Dual J-K Flip-Flop with Set and Reset

文件大小

39.33 Kbytes

頁面數(shù)量

2

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-8 22:50:00

ACS109D規(guī)格書詳情

Radiation Hardened Dual J-K Flip-Flop with Set and Reset

The Radiation Hardened ACS109MS is a Dual J-K Flip Flop with Set and Reset. These Flip-Flops have independent J, K, Set, Reset, and Clock inputs and Q and Q outputs. The outputs change state on the positive-going transition of the clock. Set and Reset are accomplished asynchronously by Low-level inputs. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times.

Features

? QML Qualified Per MIL-PRF-38535 Requirements

? 1.25 Micron Radiation Hardened SOS CMOS

? Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)

? Input Logic Levels. . . . VIL= (0.3)(VCC), VIH= (0.7)(VCC)

? Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)

? Quiescent Supply Current . . . . . . . . . . . . . . . 10μA (Max)

? Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns (Max)

Applications

? High Speed Control Circuits

? Sensor Monitoring

? Low Power Designs

產(chǎn)品屬性

  • 型號(hào):

    ACS109D

  • 制造商:

    INTERSIL

  • 制造商全稱:

    Intersil Corporation

  • 功能描述:

    Radiation Hardened Dual J-K Flip-Flop with Set and Reset

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