8P34S1208集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

Description

The 8P34S1208 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of 1PPS signals or

high-frequency, very low additive phase-noise clock and data

signals.

The 8P34S1208 supports fail-safe operation and is

characterized to operate from a 1.8V or 2.5V power supply.

Guaranteed output-to-output and part-to-part skew

characteristics make the 8P34S1208 ideal for those clock

distribution applications demanding well-defined performance

and repeatability. Two selectable differential inputs and eight

low skew outputs are available. The integrated bias voltage

reference enables easy interfacing of single-ended signals to

the device inputs. The device is optimized for low power

consumption and low additive phase noise.

Features

? Eight low skew, low additive jitter LVDS output pairs

? Two selectable, differential clock input pairs

? Differential CLK, nCLK pairs can accept the following

differential input levels: LVDS, CML

? Maximum input clock frequency: 1.5GHz

? LVCMOS/LVTTL interface levels for the control input select pin

? Output skew: 20ps (typical)

? Propagation delay: 400ps (maximum)

? Low propagation delay variation across temperature for 1PPS

applications

? Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

12kHz–20MHz: 34fs (typical)

? Device current consumption (IDD):

? 120mA typical: 1.8V

? 132mA typical: 2.5V

? Full 1.8V or 2.5V supply voltage

? Lead-free (RoHS 6), 28-Lead VFQFPN packaging

? -40°C to +85°C ambient operating temperature

? Supports case temperature up to +105°C

? Supports PCI Express Gen 1-5