854S204BGILF

Marking：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features ?TwoprogrammabledifferentialLVDSorLVPECLoutputbanks ?Twodifferentialclockinputpairs ?PCLKx,nPCLKxpairscanacceptthefollowingdifferential inputlevels:LVDS,LVPECL,SSTL,CML ?Maximumoutputfrequency:3GHz ?TranslatesanysingleendedinputsignaltoLVDSleve

854S204BGILF

Marking：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

854S204BGILFT

Marking：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features ?TwoprogrammabledifferentialLVDSorLVPECLoutputbanks ?Twodifferentialclockinputpairs ?PCLKx,nPCLKxpairscanacceptthefollowingdifferential inputlevels:LVDS,LVPECL,SSTL,CML ?Maximumoutputfrequency:3GHz ?TranslatesanysingleendedinputsignaltoLVDSleve

854S204BGILFT

Marking：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

854S204BGILFT

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動器 描述：IC CLK BUFFER 1:2 3GHZ 16TSSOP

Renesas Electronics America Inc

ICS854S204AGILF

LOWSKEW,DUAL,PROGRAMMABLE1-TO-2DIFFERENTIALTO-LVDS,LVPECLFANOUTBUFFER

GENERALDESCRIPTION TheICS854S204Iisalowskew,highperformancedual,programmable1-to-2Differential-to-LVDS,LVPECLFanoutBufferandamemberoftheHiPerClockS?familyofHighPerformanceClockSolutionsfromIDT.ThePCLKx,nPCLKxpairscanacceptmoststandarddifferentialinputlevels.

ICS854S204BGILF

LOWSKEW,DUAL,PROGRAMMABLE1-TO-2DIFFERENTIALTO-LVDS,LVPECLFANOUTBUFFER

GENERALDESCRIPTION TheICS854S204Iisalowskew,highperformancedual,programmable1-to-2Differential-to-LVDS,LVPECLFanoutBufferandamemberoftheHiPerClockS?familyofHighPerformanceClockSolutionsfromIDT.ThePCLKx,nPCLKxpairscanacceptmoststandarddifferentialinputlevels.

ICS854S204BGILFT

LOWSKEW,DUAL,PROGRAMMABLE1-TO-2DIFFERENTIALTO-LVDS,LVPECLFANOUTBUFFER

GENERALDESCRIPTION TheICS854S204Iisalowskew,highperformancedual,programmable1-to-2Differential-to-LVDS,LVPECLFanoutBufferandamemberoftheHiPerClockS?familyofHighPerformanceClockSolutionsfromIDT.ThePCLKx,nPCLKxpairscanacceptmoststandarddifferentialinputlevels.

ICS854S204I

LowSkew,Dual,Programmable1-to-2Differential-to-LVDS,LVPECLFanoutBuffer

ICS854S204I

LowSkew,Dual,Programmable1-to-2Differential-to-LVDS,LVPECLFanoutBuffer

Features ?TwoprogrammabledifferentialLVDSorLVPECLoutputbanks ?Twodifferentialclockinputpairs ?PCLKx,nPCLKxpairscanacceptthefollowingdifferential inputlevels:LVDS,LVPECL,SSTL,CML ?Maximumoutputfrequency:3GHz ?TranslatesanysingleendedinputsignaltoLVDSleve