FEATURES

· 4 channel CODEC with on-chip digital filters

· Selectable A-law or m-law companding

· Master clock frequency selection: 2.048 MHz, 4.096 MHz or

8.192 MHz

- Internal timing automatically adjusted based on MCLK and frame

sync signal

· Separate PCM and master clocks

· Single PCM port with up to 8.192 MHz data rate (128 time slots)

· Transhybrid balance impedance hardware adjustable via external

components

· Transmit gains hardware adjustable via external components

· Low power +5.0 V CMOS technology

· +5.0 V single power supply

· Package available: 32 pin PLCC

DESCRIPTION

The 821004J is a single-chip, four channel PCM CODEC with on-chip

filters. The device provides analog-to-digital and digital-to-analog

conversions and supports both a-law and m-law companding. The digital

filters in 821004J provides the necessary transmit and receive filtering for

voice telephone circuit to interface with time-division multiplexed systems.

All of the digital filters are performed in digital signal processors operating

from an internal clock, which is derived from MCLK. The fixed filters set

the transmit and receive gain and frequency response.

In the 821004J the PCM data is transmitted to and received from the

PCM highway in time slots determined by the individual Frame Sync signals

(FSRn

and FSXn

, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both

Long and Short Frame Sync modes are available in the 821004J.

The 821004J can be used in digital telecommunication applications

such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/

Data Access Unit.

821004J屬于集成電路（IC） > 編解碼器。瑞薩科技有限公司制造生產(chǎn)的821004J編解碼器編解碼器是用于通過(guò)壓縮和解壓縮來(lái)轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲(chǔ)空間。某些編解碼器提供高達(dá) 32 位的分辨率，并且分別提供多達(dá) 6 個(gè)或 8 個(gè)模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。