1. General description

The 74LVT16244B; 74LVTH16244B is a 16-bit buffer/line driver with 3-state outputs. The device

can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four

output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on

nOE causes the outputs to assume a high-impedance OFF-state. Bus hold data inputs eliminate

the need for external pull-up resistors to define unused inputs

2. Features and benefits

? 16-bit bus interface

? 3-state buffers

? Wide supply voltage range from 2.7 to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? BiCMOS high speed and output drive

? Output capability: +64 mA and -32 mA

? Direct interface with TTL levels

? Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

? Power-up 3-state

? Live insertion and extraction permitted

? No bus current loading when output is tied to 5 V bus

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

? Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to 85 °C

74LVTH16244BDGG屬于集成電路（IC） > 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74LVTH16244BDGG緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。